Skip to main navigation Skip to search Skip to main content

Static Communication Analysis for Hardware Design

Research output: Chapter in Book/Report/Conference proceedingArticle in proceedingsResearchpeer-review

28 Downloads (Pure)

Abstract

Hardware acceleration of algorithms is an effective method for improving performance in high-demand computational tasks. However, developing hardware designs for such acceleration fundamentally differs from software development, as it requires a deep understanding of the highly parallel nature of the hardware architecture. In this paper, we present a framework for the static analysis of communication within datapath architectures designed for field-programmable gate arrays (FPGAs). Our framework aims to enhance hardware design and optimization by providing insights into communication patterns within the architecture, which are essential for ensuring efficient data handling.
Original languageEnglish
Title of host publicationProceedings 16th International Workshop on Programming Language Approaches to Concurrency and Communication-cEntric Software : Hamilton, Canada, 4th May 2025
EditorsFarzaneh Derakhshan, Jan Hoffmann
Number of pages10
PublisherEPTCS
Publication date27 May 2025
Pages34-43
DOIs
Publication statusPublished - 27 May 2025
Event16th International Workshop on
Programming Language Approaches to Concurrency and Communication-cEntric Software
- Hamilton, Canada
Duration: 4 May 20254 May 2025
Conference number: 16

Workshop

Workshop16th International Workshop on
Programming Language Approaches to Concurrency and Communication-cEntric Software
Number16
Country/TerritoryCanada
CityHamilton
Period04/05/202504/05/2025
SeriesElectronic Proceedings in Theoretical Computer Science, EPTCS
Volume420
ISSN2075-2180

Keywords

  • Datapath architecture
  • Hardware description language
  • Static analysis

Citation Styles