Abstract
Hardware acceleration of algorithms is an effective method for improving performance in high-demand computational tasks. However, developing hardware designs for such acceleration fundamentally differs from software development, as it requires a deep understanding of the highly parallel nature of the hardware architecture. In this paper, we present a framework for the static analysis of communication within datapath architectures designed for field-programmable gate arrays (FPGAs). Our framework aims to enhance hardware design and optimization by providing insights into communication patterns within the architecture, which are essential for ensuring efficient data handling.
| Original language | English |
|---|---|
| Title of host publication | Proceedings 16th International Workshop on Programming Language Approaches to Concurrency and Communication-cEntric Software : Hamilton, Canada, 4th May 2025 |
| Editors | Farzaneh Derakhshan, Jan Hoffmann |
| Number of pages | 10 |
| Publisher | EPTCS |
| Publication date | 27 May 2025 |
| Pages | 34-43 |
| DOIs | |
| Publication status | Published - 27 May 2025 |
| Event | 16th International Workshop on Programming Language Approaches to Concurrency and Communication-cEntric Software - Hamilton, Canada Duration: 4 May 2025 → 4 May 2025 Conference number: 16 |
Workshop
| Workshop | 16th International Workshop on Programming Language Approaches to Concurrency and Communication-cEntric Software |
|---|---|
| Number | 16 |
| Country/Territory | Canada |
| City | Hamilton |
| Period | 04/05/2025 → 04/05/2025 |
| Series | Electronic Proceedings in Theoretical Computer Science, EPTCS |
|---|---|
| Volume | 420 |
| ISSN | 2075-2180 |
Keywords
- Datapath architecture
- Hardware description language
- Static analysis
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