Language Support for Implementing Algorithms on Low Level Hardware Components

Future optimizations of algorithms will include hardware implementations targeting a field-programmable gate array (FPGA). However, describing hardware in a hardware description language like VHDL or Verilog is cumbersome compared to describing an algorithm in a software language like C or Java. An alternative is to use High-level synthesis to convert programs in C into hardware design.

We explore language extensions that can assist programmers in designing algorithms for FPGA components and be integrated into existing hardware designs. The aim is to give the programmer control over the parallelism while retaining the algorithmic aspects in the development process. We compare hardware designs generated using the language extensions with designs written directly in hardware description languages.